8991 Cpu Gate Level Synthesis Engineer jobs in Santa Clara,CA

Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics Co.

San Jose, CA 95123

10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD
Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
Demonstrated successful architectural through RTL design experience on high performance digital designs
Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Knowledge of system caches and directory snoop filter protocols.
Familiarity with different on-chip network topologies: mesh, ring, crossbar.
Experience in leading and mentoring a team of engineers.
Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
Knowledge of memory subsystem design including coherent cache design.

Apple, Inc.

Cupertino, CA 95014

Adecco

Santa Clara, CA 95051

Associate degree or higher in manufacturing or mechanical engineering
Experience with hand tools (screwdrivers, torque drivers, wrenches, pliers, etc.)
Soldering experience
PCBA (through-hole and SMT) certifications/experience
Fabrication skills (e.g., hand drill, drill press)
Familiarity with production and lean principles
Strong verbal and written communication skills
Ability to convey complex information and build consensus