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Asic Verification Engineer

Sunnyvale,CA

1626 Asic Verification Engineer jobs in Sunnyvale,CA

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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

Annapurna Labs (U.S.)

Cupertino, CA 95014

~ 12 min OnsiteUrgently HiringHealth InsurancePaid Time OffRetirement Benefit

  • Bachelor's degree in Electrical Engineering or a related field
  • Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills
  • Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
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Sr. Principal Systems Engineer Level 4

Northrop Grumman

Sunnyvale, CA 94087

OnsiteHealth InsurancePaid Time Off

  • Bachelor's Degree in a STEM (Science, Technology, Engineering or Math) discipline with 8 years relevant experience; or Master's Degree in a STEM (Science, Technology, Engineering or Math) discipline with 6 years relevant work experience, or PhD with 4 years of experience.
  • Ability to read and interpret technical drawings
  • First-hand experience with requirements and interface management
  • Familiarity with system drawings and documents such as Interface Control Documents, System/Subsystem Specifications, Verification Cross Reference Matrices (VCRM), etc.
  • Experience with system engineering tools such as IBM Rational DOORS
  • Familiarity with MBE/MBSE concepts and tools
  • Must be a US citizen
  • Must be able to obtain and maintain a US Government Secret Clearance
  • TRAVEL: Yes, 10% of the Time
  • CLEARANCE TYPE: Secret
  • RELOCATION ASSISTANCE: Relocation assistance may be available
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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

Annapurna Labs (U.S.)

Cupertino, CA 95014

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Combat Engineer - Find Success in US Army

US ARMY

Monterey, CA 93940

Requires TravelEducation AssistanceHealth InsurancePaid Time Off

  • Attend a 14-week paid training program to gain skills and certifications in construction, engineering, demolition, and heavy equipment operations.
  • Advanced certifications require additional full funded training programs.
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Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics Co.

San Jose, CA 95123

~ 20 min OnsiteEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

  • 6+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 4+ years of experience with a Master's degree, or 2+ years of experience with a PhD
  • Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
  • Demonstrated successful architectural through RTL design experience on high performance digital designs
  • Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
  • Knowledge of system caches and directory snoop filter protocols.
  • Familiarity with different on-chip network topologies: mesh, ring, crossbar.
  • Experience in leading and mentoring a team of engineers.
  • Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
  • Knowledge of memory subsystem design including coherent cache design.
  • Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.
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Quality Inspector

Morgan Advanced Materials

Hayward, CA 94544

~ 36 min OnsiteHealth InsurancePaid Time OffRetirement Benefit

  • High school diploma or equivalent
  • Experience in a quality inspection role within a manufacturing environment
  • Strong understanding of blueprint and drawing interpretation, including GD&T; and ANSI Y14.5 standards
  • Hands-on experience with inspection equipment and precision measuring tools
  • Ability to create and manage inspection programs using Vertex equipment
  • Good communication skills and a collaborative approach to problem-solving
  • Ability to work with limited supervision while supporting a team environment
  • Comfortable lifting up to 35 pounds as part of normal job duties
  • Ability to meet pre-employment screening requirements
  • Eligibility to work in the United States in accordance with applicable regulations
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Systems Test Engineer Level 2 /3

Northrop Grumman

Sunnyvale, CA 94087

OnsiteHealth InsurancePaid Time Off

  • Bachelor's degree in a STEM discipline (Science, Technology, Engineering or Math) with 2+ years of relevant work; experience, or a Masters degree in a STEM discipline with 0+ years of relevant work experience
  • Exposure to test plans and procedures for mechanical systems
  • Experience participating in test meetings
  • Exposure to test reports
  • Exposure to requirement verification
  • Proficient with MS Office
  • Must be a U.S. citizen with the ability to obtain a Secret clearance
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Design For Test Engineer IV (IC)

Arrow Electronics

San Jose, CA 95110

~ 20 min OnsiteEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

  • 5 – 7 Years of experience in DFT
  • Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing)
  • MBIST Insertion and Verification
  • Experience in IEEE 1149.1 JTAG Insertion and verification
  • Scripting languages like Perl, Shell, TCL
  • Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes
  • Tools: Mentor Tessent
  • B. Tech, M.Tech in Microelectronics/Electronics
  • Low power DFT
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Combat Engineer - Entry Level

US ARMY

Monterey, CA 93940

Requires TravelEducation AssistanceHealth InsurancePaid Time Off

  • Attend a 14-week paid training program to gain skills and certifications in construction, engineering, demolition, and heavy equipment operations.
  • Advanced certifications require additional full funded training programs.
SmartExplore AI is experimental.
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STAFF MANUFACTURING ENGINEER

TE Connectivity

Milpitas, CA 95035

~ 18 min Onsite

  • BS/MS in Mechanical, Electrical, Chemical, Manufacturing, or Materials Engineering (or closely related engineering field)
  • Hands-on experience with semiconductor/MEMS wafer processing in a cleanroom environment
  • Demonstrated data driven decision making
  • Proficiency with engineering tools such as metrology equipment, wafer probing systems, SPC/DOE software (Minitab/JMP)
  • Experience with process control, formal process release, and engineering documentation (PFMEA, control plans, specifications)
  • Strong analytical and statistical skills with demonstrated use of ANOVA, SPC, DOE, or advanced data analysis methods in production environment
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