Pega Developer

San Jose,CA

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991 Pega Developer jobs in San Jose,CA

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Data Entry Clerk Work From Home - Part-Time Focus Group Participants ($750/Week)

Apex Focus Group - San Jose, CA

Apex Focus Group - San Jose, CA

Data Entry Clerk Work From Home - Part-Time Focus Group Participants ($750/Week)

$750/wk

RemoteNo Experience

Java Developer

EITAcies

Santa Clara, CA 95054

Route Driver

Sodexo

Santa Clara, CA 95054

$25/hr

~ 14 min OnsiteChat NowEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

High School Diploma or equivalent experience
Valid driver's license required
Must be at least 21 years of age
Attends work and shows for scheduled shift on time with satisfactory regularity

SmartExplore AI is experimental.

New, Posted 2 hours ago

IT JOB Training Program

Year Up United

San Jose, CA 95123

$525/wk

A high school graduate or GED recipient
Eligible to work in the U. S.
Highly motivated to learn technical and professional skills
Have not obtained a Bachelor's degree
You may be required to answer additional screening questions when applying

SmartExplore AI is experimental.

Senior Technology Development Operations Manager

Cooley LLP

Palo Alto, CA 94301

Test Software Engineer

Yoh

Sunnyvale, CA 94087

$50/hr

New, Posted 1 hour ago

Information Technology Professional (IT Support)

U.S. Navy

Santa Clara, CA 95051

New, Posted 1 day ago

Semiconductor Trainer - Course Developer

Canon U.S.A.

San Jose, CA 95153

Flexible Schedule

New, Posted 1 day ago

Mechanical Application Development Engineer

Amphenol TCS

Santa Clara, CA 95051

Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics Co.

San Jose, CA 95123

OnsiteEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD
Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
Demonstrated successful architectural through RTL design experience on high performance digital designs
Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Knowledge of system caches and directory snoop filter protocols.
Familiarity with different on-chip network topologies: mesh, ring, crossbar.
Experience in leading and mentoring a team of engineers.
Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
Knowledge of memory subsystem design including coherent cache design.

SmartExplore AI is experimental.

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89% of jobs ask for a resume

Don't let the perfect job slip away—upload your resume and we'll personalize your results instantly.

Human Resources Manager

Superior Court Of California County Of Santa Clara

San Jose, CA 95113

$127,194-$170,452/yr

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