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Debug

San Jose,CA

780 Debug jobs in San Jose,CA

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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

Annapurna Labs (U.S.)

Cupertino, CA 95014

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Sr. System RTL Designer/Serdes Architect

Advanced Micro Devices

San Jose, CA 95124

Hybrid

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
SmartExplore AI is experimental.
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New, Posted 16 hours ago
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Sr Principal TIA Designer

Nokia

Sunnyvale, CA 94089

~ 19 min Onsite

  • Lead the architecture, design, simulation, verification, and silicon bring-up of ultra-high-speed Transimpedance Amplifiers (TIAs) for coherent optical and PAM4 data center applications
  • Translate system and chip-level requirements into robust analog circuit architectures and detailed transistor-level designs
  • Design and optimize low-noise, high-linearity broadband analog circuits for optical receiver front ends
  • Develop and validate supporting analog functions, including AGC loops, CTLEs, voltage regulators, bandgaps, and data converter interfaces
  • Drive package and system-level integration, ensuring optimal signal integrity and performance
  • Perform silicon characterization, debug, and correlation of measurement results against simulation models
  • Collaborate closely with layout, system, DSP, packaging, and product engineering teams throughout the development cycle
  • Lead technical reviews, contribute to design methodology improvements, and ensure successful first-pass silicon execution
  • Mentor and guide junior analog designers, fostering technical excellence within the team
  • Create and maintain high-quality technical documentation, design reports, and specifications
  • Extensive experience designing high-speed TIAs for coherent optical communication systems and/or PAM4 data center transceivers
  • Strong expertise in analog and mixed-signal IC design using SiGe BiCMOS and CMOS technologies
  • Deep understanding of transistor-level circuit design, device physics, noise analysis, and feedback/control loop stability
  • Proven experience in one or more of the following areas: Optical receiver front-end design, AGC loop implementation, CTLE design, High-precision analog circuits (bandgaps, regulators, ADC/DAC interfaces), Package and system-level integration
  • Proficiency with industry-standard EDA tools, custom analog layout techniques, and electromagnetic (EM) simulation tools
  • Demonstrated success delivering silicon from concept through production
  • Hands-on experience with lab measurement, debugging, and performance validation of high-speed ICs
  • Strong leadership, problem-solving, communication, and collaboration skills
  • Ability to work effectively in a fast-paced, multidisciplinary global engineering environment
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Staff Analog Circuit Designer

Broadcom

San Jose, CA 95123

OnsiteHealth InsurancePaid Time OffRetirement Benefit

  • Bachelor Degree plus 8+ years of related industry experience OR Master Degree plus 6+ years of related industry experience
  • Bachelor Degree + 8+ years of related industry experience OR Master Degree + 6+ years of related industry experience
SmartExplore AI is experimental.
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Design For Test Engineer IV (IC)

Arrow Electronics

San Jose, CA 95110

OnsiteEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

  • 5 – 7 Years of experience in DFT
  • Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing)
  • MBIST Insertion and Verification
  • Experience in IEEE 1149.1 JTAG Insertion and verification
  • Scripting languages like Perl, Shell, TCL
  • Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes
  • Tools: Mentor Tessent
  • B. Tech, M.Tech in Microelectronics/Electronics
  • Low power DFT
SmartExplore AI is experimental.
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Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics Co.

San Jose, CA 95123

OnsiteEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

  • 6+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 4+ years of experience with a Master's degree, or 2+ years of experience with a PhD
  • Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
  • Demonstrated successful architectural through RTL design experience on high performance digital designs
  • Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
  • Knowledge of system caches and directory snoop filter protocols.
  • Familiarity with different on-chip network topologies: mesh, ring, crossbar.
  • Experience in leading and mentoring a team of engineers.
  • Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
  • Knowledge of memory subsystem design including coherent cache design.
  • Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.
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Maintenance Technician I

SkyChefs, LLC

San Jose, CA 95123

OnsiteUrgently HiringFlexible ScheduleHealth InsuranceRetirement Benefit

  • Minimum Qualifications
  • Proven experience as a Maintenance Technician or similar role
  • Basic understanding of electrical, plumbing, HVAC, and hydraulic systems
  • Knowledge of general maintenance procedures and best practices
  • Working knowledge of hand tools, power tools, and maintenance equipment
  • Strong manual dexterity and problem-solving skills
  • Ability to work independently with minimal supervision
  • Good physical condition and ability to lift, bend, and stand for extended periods
  • Willingness to work overtime, weekends, or flexible schedules as needed
  • High school diploma or equivalent required
SmartExplore AI is experimental.
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Package Delivery - no experience required

DSPJobHub

Livermore, CA 94550

New, Posted 1 day ago
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Retail Customer Service Associate

FedEx Office

San Jose, CA 95126

$22.10-$25.97/hr
OnsiteEducation AssistanceHealth InsuranceRetirement Benefit

  • High school diploma or equivalent education
  • 6+ months of specialized experience
  • Excellent verbal and written communication skills
  • For new hires, must meet all FedEx Office employment qualifications in force at time of hiring
  • For current FedEx Office team members, must meet hiring criteria for the position and transfer requirements as outlined in the Team Member Handbook
  • Ability to stand during entire shift, excluding meal and rest periods
  • Ability to move and lift 55 pounds
  • Ability, on a consistent basis, to bend/twist at the waist and knees
  • Ability, on a consistent basis, to communicate effectively with customers, vendors, and other team members
  • Ability, on a consistent basis, to perform work activities requiring cooperation and instruction
  • Ability, on a consistent basis, to function in a fast-paced environment, under substantial pressure
  • Ability, on a consistent basis, to maintain attention and concentration for extended periods of time
  • Ability, on a consistent basis, to work with minimal supervision
  • Ability, on a consistent basis, to report regularly to work and maintain established business hours in order to support the FedEx Office business; regular attendance and/or reporting could include regular attendance at a physical location and/or maintaining established business hours depending on the scope and nature of the position
SmartExplore AI is experimental.
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