959 C++ Developer jobs in San Jose,CA

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Principal Technical Program Manager - Technical Strategy Development

Intuit

Mountain View, CA 94043

~ 21 min Onsite

7-10 years of relevant experience in delivering signiﬁcant strategic and operational impact across an organization
Proven track record in leveraging data, developing insight-backed hypotheses and driving learning plans to build compelling business cases
Demonstrated business and technical acumen, preferably in a SaaS or platform technology company
Ownership mindset with an ability to convert strategic plans into actions, drive projects to completion, and sweat the details to deliver the outcome
Experienced change management leader who is able to inﬂuence and build trust across a highly cross-functional organization (peers, executives and working teams) to accelerate outcomes
Excellent communicator with strong presentation skills and compelling storytelling abilities; feel very comfortable leading and facilitating workshops and monthly/quarterly business reviews with executives and teams
Highly self-motivated, thrives in ambiguity and able to manage multiple projects with little day to day direction
Well-rounded interpersonal skills with the capacity to build relationships with senior stakeholders and collaborate across with team members across varying levels
Ability to generate innovative insights, ideas, and opportunities that drive tangible business outcomes

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Transmission Planning Engineer

PG&E Corporation

San Jose, CA 95113

HybridUrgently Hiring

Bachelor's degree in Electrical Engineering or a related technical discipline from an accredited curriculum in the US or the equivalent from outside the US
3 years of experience in electrical engineering, planning and/or operations
EIT/PE Certification, registered Electrical Engineer in California

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Software Development Career Training Opportunity

Year Up United

San Jose, CA 95123

$525/wk

Onsite

A high school graduate or GED recipient
Eligible to work in the U. S.
Available Monday-Friday throughout the duration of the program
Highly motivated to learn technical and professional skills
Have not obtained a Bachelor's degree
You may be required to answer additional screening questions when applying

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Sr. C++ Developer

Imagry

San Jose, CA 95192

Onsite

5+ years modern C++ (C++17/20), STL / templates, multithreading / synchronization
Development of Realtime systems involving both SW & HW
2+ years of Python development
Strong Low-Level Programming and Debugging tools
Software development practices: Git, code reviews, unit tests
Experience in implementing Real-time Algorithms
B.Sc / B.A - Computer Science or other relevant university degree
Team player, with proven record of developing deployment-level products
Location: On-Site, San Jose, CA

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Turbine Design Engineer T02/T03

Northrop Grumman

Sunnyvale, CA 94087

~ 19 min OnsiteUrgently HiringHealth InsurancePaid Time Off

CLEARANCE TYPE: Top Secret
Bachelor of Science degree in a STEM (Science, Technology, Engineering, Mathematics) discipline with 2 years relevant experience; Masters of Science degree in a STEM discipline with no relevant experience.
Computer skills including developing designs using solid modeling software, such as CREO/NX is required.
A working knowledge of ANSI Y14.5 drawing standards and geometric tolerance is also necessary.
Must be fluent in mechanical engineering principles, and must be proficient in developing design concepts, performing trades-studies, and conducting supporting evaluations and analyses.
US Citizenship required.
Ability to obtain and maintain a DoD Secret level security clearance.
This position requires the candidate to be full time on-site.
TRAVEL: Yes, 10% of the Time
Bachelor of Science degree in a STEM (Science, Technology, Engineering, Mathematics) discipline with 5 years relevant experience; Masters of Science degree in a STEM discipline with 3 years relevant experience.

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Business Development – Data Center

Senko Advanced Components

Los Gatos, CA 95032

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Sr. Devops Manager

Vistance Networks

Sunnyvale, CA 94089

Hybrid~ 19 minHealth InsurancePaid Time OffRetirement Benefit

8+ years in technical operations
4+ years leading Technical Operations, SRE, or infrastructure teams
Proven track record of team development
Strong project management skills
Experience using Agile/Kanban methodologies and JIRA
Excellent communication abilities
Deep SRE experience
Infrastructure automation expertise
Terraform, Kubernetes, Docker, and CI/CD pipelines
Cloud platform proficiency in GCP/AWS
Monitoring and observability experience with Prometheus, Grafana, APM tools, and log aggregation
24/7 operations experience
On-call management, escalation procedures, and global team coordination
Change management and compliance experience with SOC2, security reviews, and audit processes
Network and systems administration background with Linux, networking protocols, and security practices

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Software Engineer for Athlete Performance Research

Another source

Palo Alto, CA 94306

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Technical Writer

Super Micro Computer

San Jose, CA 95123

Onsite

BA in English or Technical Writing
Minimum of 5+ years of experience writing technical documentation, release notes, and other technical materials for computer hardware and memory-based products and solutions
Requires extensive experience with MadCap Flare
Strong attention to detail, time management, organizational and project management skills, and ability to manage multiple projects to meet tight deadlines
Strong verbal communication skills
Ability to understand complex technical products and write for a variety of audiences in a clear, concise, consistent writing style
Ability to work under pressure and handle multiple projects and responsibilities concurrently

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Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics Co.

San Jose, CA 95123

OnsiteEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD
Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
Demonstrated successful architectural through RTL design experience on high performance digital designs
Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Knowledge of system caches and directory snoop filter protocols.
Familiarity with different on-chip network topologies: mesh, ring, crossbar.
Experience in leading and mentoring a team of engineers.
Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
Knowledge of memory subsystem design including coherent cache design.

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