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Asic Engineer

San Jose,CA

600 Asic Engineer jobs in San Jose,CA

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Nokia Logo

Nokia - Sunnyvale, CA

ASIC Manufacturing Engineer
~ 19 min OnsiteEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit
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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

Annapurna Labs (U.S.)

Cupertino, CA 95014

New, Posted 1 day ago
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Physical Design Engineer II (IC)

Arrow Electronics

San Jose, CA 95110

Onsite

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
  • 7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
  • Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
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Engineer Manufacturing / Principal Engineer Manufacturing

Northrop Grumman

Sunnyvale, CA 94087

~ 19 min OnsiteHealth InsurancePaid Time Off

  • Bachelor's degree with a minimum of 2 years of relevant work experience; OR a master's degree with 1 or more years of relevant work experience.
  • Experience reading and interpreting engineering drawings.
  • Experience with machining and machine shops.
  • Experience with mechanical assembly processes, welding and machining.
  • Experience in technical writing.
  • Ability to obtain a US Government Secret Clearance.
  • U.S. Citizenship required.
  • Ability to obtain US Government Secret Clearance.
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PD Engineer

Qualcomm

Santa Clara, CA 95050

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STAFF MANUFACTURING ENGINEER

TE Connectivity

Milpitas, CA 95035

~ 17 min Onsite

  • BS/MS in Mechanical, Electrical, Chemical, Manufacturing, or Materials Engineering (or closely related engineering field)
  • Hands-on experience with semiconductor/MEMS wafer processing in a cleanroom environment
  • Demonstrated data driven decision making
  • Proficiency with engineering tools such as metrology equipment, wafer probing systems, SPC/DOE software (Minitab/JMP)
  • Experience with process control, formal process release, and engineering documentation (PFMEA, control plans, specifications)
  • Strong analytical and statistical skills with demonstrated use of ANOVA, SPC, DOE, or advanced data analysis methods in production environment
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Mixed-Signal IC Designer

Keysight Technologies

Santa Clara, CA 95051

~ 14 min OnsiteEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

  • PhD. in Electrical Engineering or closely related field, with thesis work on mixed-signal IC design preferred, or an M.S. in Electrical Engineering with substantial experience in IC design are required
  • Experience in designing high-speed analog and mixed-signal circuits in CMOS or BiCMOS technologies
  • Experience must include both, transistor level design and physical design
  • Experience with mixed-signal building blocks and integrated systems, such as PLLs, DACs, Serializers, ADCs, or wideband amplifiers
  • Demonstrated ability to work well in a team environment, and strong ability to document and present results
  • Excellent interpersonal, problem solving, and communication skills to work in dynamic environment as part of multiple teams working on multiple projects and collaborate cross-functionally with a team-oriented mindset
  • Ability to troubleshoot, and drive to root cause on difficult problems
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New Product Manufacturing Engineer

CACI International Inc

Los Gatos, CA 95032

~ 18 min Onsite

  • BA/BS degree in a technical discipline from an accredited college or university.
  • Minimum of five (5) years of experience as a manufacturing engineer or in a related role.
  • Must be a US person.
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Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics Co.

San Jose, CA 95123

OnsiteEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

  • 6+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 4+ years of experience with a Master's degree, or 2+ years of experience with a PhD
  • Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
  • Demonstrated successful architectural through RTL design experience on high performance digital designs
  • Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
  • Knowledge of system caches and directory snoop filter protocols.
  • Familiarity with different on-chip network topologies: mesh, ring, crossbar.
  • Experience in leading and mentoring a team of engineers.
  • Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
  • Knowledge of memory subsystem design including coherent cache design.
  • Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.
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New, Posted 8 hours ago
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Software Engineer - Data Protection Software Engineering

Dell

Santa Clara, CA 95050

~ 14 min Onsite

  • Software Engineer 2
  • Santa Clara, California
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