898 Synopsys jobs in Mountain View,CA

Bachelor's Degree in STEM (Science, Technology, Engineering or Math) discipline with 2 years relevant work experience; or Master's Degree in STEM (Science, Technology, Engineering or Math) with no relevant experience.
Experience in frequency domain analysis.
Experience characterizing and analyzing system stability.
Experience with block diagrams and linear algebra.
Experience with grey-box model validation.
Proficiency with MATLAB coding and Simulink modeling.
Experience building state space models of multiphysical systems.
Experience with numerical methods for solving differential equations.
Must be a US citizen.
Ability to obtain and maintain a US Government Secret Clearance.
Must be onsite 4 days a week, remote work is not an option for this role.

Teledyne

Mountain View, CA 94040

B.S. Engineering degree
0-2 years of electronics of hardware manufacturing experience (internships welcomed)
Strong analytical and troubleshooting skills
Hands-on aptitude with fine-pitch electronics and lab equipment
Clear written and verbal communication skills
U.S. citizenship and ability to obtain security clearance

CLEAR

San Jose, CA 95110

Must be 18 years of age or older.
High school diploma or GED equivalent required.
Completion of all required airport and government security screening processes, including SIDA badge eligibility. This may also include federal Personnel Security (PerSec) SF-85 screening, depending on your work assignment.
SF-85 background check may be adjudicated by the Department of Homeland Security and may include additional criminal screening, credit checks, and verification of identity and citizenship or immigration status, as required by federal security screening standards.

PG&E Corporation

Mountain View, CA 94041

Samsung Electronics Co.

San Jose, CA 95123

10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD
Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
Demonstrated successful architectural through RTL design experience on high performance digital designs
Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Knowledge of system caches and directory snoop filter protocols.
Familiarity with different on-chip network topologies: mesh, ring, crossbar.
Experience in leading and mentoring a team of engineers.
Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
Knowledge of memory subsystem design including coherent cache design.