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Quality Engineer

Capitola,CA

520 Quality Engineer jobs in Capitola,CA

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Power Supply Quality Manager

Super Micro Computer - San Jose, CA

Super Micro Computer - San Jose, CA

Power Supply Quality Manager
~ 42 min Onsite
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Wafer Manufacturing Equipment Engineer

Western Digital

San Jose, CA 95123

~ 42 min OnsiteUrgently HiringEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

  • Technical degree in Electronics, Military experience, or Semiconductor Industries experience.
  • Must have excellent mechanical and electrical aptitude.
  • Min 0-5+ Years' Experience in Vacuum, Photo, or Wet/Plating Technologies.
  • Ability to read electrical schematic diagrams and assembly drawings.
  • Understanding of failure mechanisms, ability to isolate determine root cause and repair.
  • Proficient in MS Office Applications (Word/Excel/Power Point/Outlook), Mediawiki
  • Programming languages in PLC, Python, HTML, JavaScript a plus.
  • Effective team player with proven relationship building & communication skills, including cross-functionally with Maintenance, Manufacturing, Engineering, Peers, Management, Customers, and Suppliers.
  • Knowledge of control systems and/or PLC (Process Logic Control)
  • Ability to work overtime and weekends as required.
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12B1 Combat Engineer - Start Your Career with the US Army

U.S. Army

Monterey, CA 93940

~ 39 min OnsiteUrgently HiringEducation AssistanceHealth InsurancePaid Time Off

  • Attend a 14-week paid training program to gain skills and certifications in construction, engineering, demolition, and heavy equipment operations.
  • Advanced certifications require additional full funded training programs.
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Data and Visualization Engineer

BOOZ, ALLEN & HAMILTON

Monterey, CA 93940

RemoteUrgently HiringEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

  • 2+ years of experience with data analysis
  • 2+ years of experience with data visualization
  • 2+ years of experience with data pipeline engineering
  • Experience with programming languages, including Python, R, or SQL, for data manipulation and analysis
  • Experience working in Foundry, including building or maintaining data pipelines with Code Repository
  • Knowledge of database-driven application development and design
  • Ability to develop and maintain interactive dashboards and visualizations in Foundry, Power BI, Tableau, or Qlik to communicate data insights to business stakeholders
  • Ability to collaborate with business analysts or users to clarify requirements, work closely with different business groups to comprehend and respond to their reporting and dashboard needs, and be self-motivated
  • Secret clearance
  • Bachelor's degree
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Transmission Planning Engineer

PG&E Corporation

San Jose, CA 95113

Hybrid~ 42 minUrgently Hiring

  • Bachelor's degree in Electrical Engineering or a related technical discipline from an accredited curriculum in the US or the equivalent from outside the US
  • 3 years of experience in electrical engineering, planning and/or operations
  • EIT/PE Certification, registered Electrical Engineer in California
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New, Posted 7 hours ago
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DiversityJobs
Sr. QA Engineer - IP Routing

CIENA

San Jose, CA 95113

Flexible Schedule
New, Posted just now
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Test System Design Engineer

Circuit Check

San Jose, CA 95123

New, Posted 8 hours ago
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Principal Quality Operations Specialist - Location Flexible

PG&E Corporation Careers

Capitola, CA 95010

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Nuclear Engineer

U.S. Navy

Capitola, CA 95010

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Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics Co.

San Jose, CA 95123

~ 42 min OnsiteUrgently HiringEducation AssistanceHealth InsurancePaid Time OffRetirement Benefit

  • 10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD
  • Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
  • Demonstrated successful architectural through RTL design experience on high performance digital designs
  • Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
  • Knowledge of system caches and directory snoop filter protocols.
  • Familiarity with different on-chip network topologies: mesh, ring, crossbar.
  • Experience in leading and mentoring a team of engineers.
  • Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
  • Knowledge of memory subsystem design including coherent cache design.
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